Trellis coded modulation tails

ABSTRACT

An encoder includes a state machine configured to generate a payloads as a function of a state machine output, and an interface configured to generate a tail as a function of a binary representation of the state machine output at the end of the payload generation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority under 35 U.S.C. § 119(e)to provisional Application No. 60/272182, filed Feb. 28, 2001, entitled“TRELLIS CODED MODULATION TAILS” which is expressly incorporated hereinby reference as though fully set forth in full.

FIELD OF THE INVENTION

[0002] The present invention relates to telecommunication systems, andin particular, to Trellis tails appended at the end of frames of TrellisCoded Modulation encoded information.

BACKGROUND

[0003] Communication systems are used for transmission of informationfrom one device to another. The devices included in the communicationsystem typically have either a transmitter, a receiver, or both. Beforetransmission, information is encoded by a transmitter's encoder into aformat suitable for transmission over a communication channel. Thecommunication channel may be a transmission line or the free spacebetween the transmitting device and the receiving device. As the signalpropagates through the communication channel, the transmitted signal isdistorted by imperfections in the channel. Furthermore, the signalexperiences degradation from noise and interference picked up duringtransmission. After the receiver receives the encoded information, it isdecoded and translated into its original pre-encoded form. Both thetransmitter and receiver are designed to minimize the effects of channelimperfections, noise, and distortion.

[0004] One widely used method of reducing the effects of channelimperfections, noise, and distortion in high speed communication systemsis encoding digital information using Trellis Coded Modulation (TCM).TCM encoding schemes assign a coded binary value to digital informationsignals input to the transmitter's encoder. The coded binary value isdetermined based upon the bits that make up the information signal andthe bits that represent the current state of a finite state machine(FSM), an electronic circuit that implements a restricted sequence ofstates, included in the transmitter's encoder. Thus, the TCM encodergenerates a restricted sequence of coded binary values based on theFSM's states. Since the TCM encoding scheme is dependent upon an FSM,the complexity of encoding scheme depends upon the number of statessupported by the particular FSM.

[0005] The device that receives the encoded information includes areceiver having a Maximum Likelihood Sequence Decoder (MLSD) which maybe, for example, a Viterbi decoder. The receiver receives the encodedinformation and analyzes it using the MLSD. The MLSD compares thereceived encoded information to all of the possible encoding sequencesthat could be generated by the transmitter's encoder and then decideswhat was the most likely sequence sent by the encoder. The MLSD thendecodes the encoded information based upon the most likely sequence.

[0006] Digital information that passes through a communication systemcan vary in length. Encoded digital information is grouped into stringsof bits called frames. In some communication systems the number of bitsincluded in each frame is fixed, while in others the number of bits isvariable. TCM is equally suitable for encoding data organized in framesof fixed or variable lengths. Also, TCM can be equally applied to bothburst transmissions or continuous-type transmissions.

[0007] Included in a typical frame of TCM encoded informationconstituting a burst transmission is; a preamble, a data payload, acyclic redundancy code (CRC), and a Trellis tail. The preamble is astring of bits sent by the transmitter that are also stored in thereceiver. The receiver compares the received preamble to the storedpreamble, and via this comparison, determines information related to thechannel, i.e., gain control information, carrier-frequency offsetinformation, signal timing adjustment information, and channelestimation information that is utilized by the receiver when decodingthe received signal. The data payload is the encoded version of theinformation that was input to the transmitter's encoder. The CRC is usedto determine if any of the bits transmitted in the frame of data werereceived in error. The CRC is the remainder generated by dividing apolynomial that represents the entire frame of information by a divisorstored in the encoder. The receiver takes the received frame and againrepresents it as a polynomial and divides the polynomial by the samedivisor stored in the encoder. Next, the receiver compares the resultingremainder with the CRC and determines if the received signal is inerror.

[0008] As stated previously, the receiver's MLSD decodes the encodedinformation based upon a determination of the most likely sequence ofstates used to encode the information. In order for the MLSD to workproperly for all of the encoded information in the frame, the frame hasto end at a known state. Thus, for burst transmissions, the MLSD may notbe able to accurately decode the encoded information. In order to avoidthis problem associated with burst transmissions, each frame oftransmitted information includes a string of bits called a “Trellistail” that is appended at the end of each frame. The bits that make upthe Trellis tail are merely used to make sure that the MLSD is providedwith a sequence that ends at a known state, thus, facilitating accuratedecoding.

[0009] The string of bits that make up the Trellis tail can differsignificantly depending upon the type of encoder used, the number of FSMstates utilized by the encoder, and the known ending state of thesequence. Because the Trellis tail may be implemented in many differentways, the string of bits that make up the Trellis tail must be stored inmemory and later accessed during the encoding and decoding processes.Therefore, in general, TCM encoding schemes used for burst transmissionshave the distinct disadvantage of requiring dedicated memory for storageof the bits that make up the Trellis tail.

SUMMARY

[0010] In one aspect of the present invention, an encoder includes astate machine configured to generate a plurality of state bits, and aninterface configured to couple an input relating to one of the statebits into the state machine during a time period.

[0011] In another aspect of the present invention, an encoder includesstate generation means for generating a plurality of state bits, andinterface means for coupling an input relating to one of the state bitsinto the state generation means during a time period.

[0012] In yet another aspect of the present invention, a transmitterhaving an encoder having, a state machine configured to generate aplurality of state bits, and an interface configured to couple an inputrelating to one of the state bits into the state machine during a timeperiod, and an RF stage coupled to the encoder.

[0013] In a further aspect of the present invention, a transmitterincluding an encoder having, state generation means for generating aplurality of state bits, and interface means for coupling an inputrelating to one of the state bits into the state generation means duringa time period, and an RF stage coupled to the encoder.

[0014] In yet a further aspect of the present invention, a encoderincludes a state machine configured to generate a state, and aninterface configured to serially couple an input relating to a binaryrepresentation of the state into the state machine during a time period.

[0015] In another aspect of the present invention, an encoder includesstate generation means for generating a state, and interface means forserially coupling an input relating to a binary representation of thestate into the state machine during a time period.

[0016] In yet another aspect of the present invention, a method ofgenerating a signal includes generating a payload as a function of astate machine output, generating a tail as a function a binaryrepresentation of the state machine output at the end of the payloadgeneration, and appending the tail to the payload.

[0017] It is understood that other aspects of the present invention willbecome readily apparent to those skilled in the art from the followingdetailed description, wherein is shown and described only exemplaryembodiments of the invention, simply by way of illustration of the bestmode contemplated for carrying out the invention. As will be realized,the invention is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the invention. Accordingly, thedrawings and description are to be regarded as illustrative in nature,and not as restrictive.

DESCRIPTION OF THE DRAWINGS

[0018] These and other features, aspects, and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings where:

[0019]FIG. 1 is a block diagram of a transmitter having a TCM encoder inaccordance with an exemplary embodiment of the present invention;

[0020]FIG. 2 is a diagram of a data structure including a Trellis tailin accordance with an exemplary embodiment of the present invention;

[0021]FIG. 3 is a block diagram of a TCM encoder having a 4-state FSM inaccordance with an exemplary embodiment of the present invention;

[0022]FIG. 4 is a state table for the 4-state FSM depicted in FIG. 3 inaccordance with an exemplary embodiment of the present invention;

[0023]FIG. 5 is a Trellis diagram for the 4-state FSM depicted in FIG. 3in accordance with an exemplary embodiment of the present invention;

[0024]FIG. 6 is a block diagram of a TCM encoder having an 8-state FSMin accordance with an exemplary embodiment of the present invention;

[0025]FIG. 7 is a state table for the 8-state FSM depicted in FIG. 6 inaccordance with an exemplary embodiment of the present invention;

[0026]FIG. 8 is a Trellis diagram for the 8-state FSM depicted in FIG. 6in accordance with an exemplary embodiment of the present invention;

[0027]FIG. 9 is a Trellis diagram of a Trellis tail for the 4-state FSMdepicted in FIG. 3 in accordance with an exemplary embodiment of thepresent invention;

[0028]FIG. 10 is a table of the bits constituting the Trellis tail ofFIG. 9 in accordance with an exemplary embodiment of the presentinvention;

[0029]FIG. 11 is a block diagram of a TCM encoder with feedback havingan 4-state FSM in accordance with an exemplary embodiment of the presentinvention;

[0030]FIG. 12 is a Trellis diagram of a Trellis tail for the 4-state FSMdepicted in FIG. 11 in accordance with an exemplary embodiment of thepresent invention;

[0031]FIG. 13 is a table of the bits constituting the Trellis tail ofFIG. 12 in accordance with an exemplary embodiment of the presentinvention;

[0032]FIG. 14 is a Trellis diagram of a Trellis tail for the 8-state FSMdepicted in FIG. 6 in accordance with an exemplary embodiment of thepresent invention;

[0033]FIG. 15 is a table of the bits constituting the Trellis tail ofFIG. 14 in accordance with an exemplary embodiment of the presentinvention;

[0034]FIG. 16 is a block diagram of a TCM encoder with feedback havingan 8-state FSM in accordance with an exemplary embodiment of the presentinvention;

[0035]FIG. 17 is a Trellis diagram of a Trellis tail for the 8-state FSMdepicted in FIG. 16 in accordance with an exemplary embodiment of thepresent invention; and

[0036]FIG. 18 is a table of the bits constituting the Trellis tail ofFIG. 17 in accordance with an exemplary embodiment of the presentinvention.

DETAILED DESCRIPTION

[0037]FIG. 1 is a block diagram that illustrates an exemplary embodimentof a communications system. In particular, FIG. 1 illustrates a datasource 10, a control information source 12, and a transmitter 14. Thetransmitter includes a CRC generator 16, a TCM encoder 18, a transmitcontrol unit 20, a preamble generator 22, a switch 24, and an RF stage26. The data source is coupled to the CRC generator. The CRC generatoris coupled to the TCM encoder. The TCM encoder is coupled to the RFstage via the switch which may be a multiplexer. The control informationsource is coupled to the transmit control unit which in turn is coupledto the CRC generator, the TCM encoder, the preamble generator, and theswitch. Furthermore, the preamble generator is coupled to the switch.

[0038] Referring additionally to FIG. 2, an exemplary data structurethat can be generated via the transmitter 14 of FIG. 1, in operation,the control information source 12 sends control information signals tothe transmit control unit 20. The transmit control unit converts thecontrol information signals into signals that are sent to the CRCgenerator 16, the TCM encoder 18, the preamble generator 22, and theswitch 24. Next, the data source 10 sends a string of bits called a datapayload 28 to the CRC generator which generates a string of bits, calledthe CRC 30. The CRC generator appends the string of bits that comprisethe CRC to the string of bits that comprise the data payload and sendsthe entire string of bits to the TCM encoder. The TCM encoder encodesthe entire string of bits and appends another string of bits called a“Trellis tail” 32, which will be discussed in greater detail later inthis detailed description. The string of bits that make up the datapayload, CRC, and Trellis tail are fed into one of the switch inputs.Also, the transmit control unit sends signals to the preamble generatorwhich generates another string of bits called a preamble 34. Thepreamble is fed into the other input of the switch. The switch under thecontrol of the transmit control unit sequentially selects the string ofbits that make up the preamble followed by the string of bits thatcomprise the data payload, CRC, and Trellis tail. The resulting stringof bits, including the preamble, data payload, CRC, and Trellis tail iscalled a frame 36 which is sent to the RF stage 26 where the string ofbits is modulated with a radio frequency signal prior to transmission.

[0039]FIG. 3 is a block diagram that illustrates an exemplary embodimentof a TCM encoder 18, The TCM encoder generates a double-bit encodedoutput signal comprised of bits Z_(n) ¹ and Z_(n) ⁰ which aretransmitted from the transmitter 14. The 4-state FSM can be implementedusing two single-bit wide delay registers 42 and 44 and an adder 46.Each single-bit wide delay register delays the signal input to the delayregister by one clock cycle, represented by the letter “T.” FIG. 3 alsoshows the bits S_(n) ¹ and S_(n) ⁰ that represent the current state ofthe 4-state FSM. S_(n) ¹ is the most significant bit and S_(n) ⁰ is theleast significant bit of the current state.

[0040] In operation, a single-bit data signal X_(n) ⁰, that is part ofthe data payload 28, is fed into the TCM encoder 38. The input signalbit X_(n) ⁰ also becomes the most significant bit Z_(n) ¹ of the encodedoutput signal. Also, the least significant output bit Z_(n) ⁰ equals theleast significant current state bit S_(n) ⁰ which the 4-state FSM 40equates to the sum of the input bit X_(n) ⁰ and the most significantcurrent state bit S_(n) ¹ delayed by one clock cycle as a result of thesingle-bit wide delay register 44. Furthermore, the S_(n) ¹ bit equalsthe S_(n) ⁰ bit delayed by one clock cycle as a result of the single-bitwide delay register 42.

[0041]FIG. 4 is a table which lists the current state bits 50 of the4-state FSM 40 represented by S_(n) ¹ and S_(n) ⁰, the input signal bit52 represented by X_(n) ⁰, the output signal bits 54 represented byZ_(n) ¹ and Z_(n) ⁰, and the next state bits 56 of the 4-state FSMrepresented by S_(n+1) ¹ and S_(n+1) ⁰. In operation, the 4-state FSMgenerates its next state, represented by bits S_(n+1) ¹ and S_(n+1) ⁰,based upon the input signal bit X_(n) ⁰ and the bits S_(n) ¹ and S_(n) ⁰that represent the current state of the 4-state FSM. For example, if thecurrent state of the 4-state FSM as reflected by bits S_(n) ¹ and S_(n)⁰ is {1 0}, and the input signal bit X_(n) ⁰ is {1}, the output signalbits Z_(n) ¹ and Z_(n) ⁰ are {1 0}, and the next state of the 4-stateFSM reflected by bits S_(n+1) ¹ and S_(n+1) ⁰ is {0 0}. FIG. 4 alsoindicates the limitations on change of state within the 4-state FSM fromthe current state represented by bits S_(n) ¹ and S_(n) ⁰ to the nextstate represented by bits S_(n+1) ¹ and S_(n+1) ⁰. For example, if thecurrent state of the 4-state FSM is {0 0}, then the next state can onlybe {0 0} if the input signal bit X_(n) ⁰ is {0}, or {0 1} if the inputsignal bit X_(n) ⁰ is {1}.

[0042] The limitation on the change of state in the 4-state FSM 40 isfurther represented in the Trellis diagram shown in FIG. 5. In FIG. 5,each of the states of the 4-state FSM is given a separate alphanumericidentifier comprised of the letter “S” and a decimal number which equalsthe binary representation of the state. The identifier S0 58 is assignedto state {0 0}, the identifier S1 60 is assigned to state {0 1}, theidentifier S2 62 is assigned to state {1 0}, and the identifier S3 64 isassigned to state {1 1}.

[0043] Starting from the left-hand side of FIG. 5, adjacent to thealphanumeric identifiers, is the first vertical column of dots whichrepresent the states of the 4-state FSM 40 at time T₀. Moving to theright, the next vertical column of dots represents the states of the4-state FSM at time T₁ which is one clock cycle after T₀. Similarly, thenext vertical column of dots to the right represents the states of the4-state FSM at time T₂ which is two clock cycles after T₀. The verticalcolumn of dots furthest to the right in FIG. 5 represent the states ofthe 4-state FSM at time T₃ which is three clock cycles after T₀. Thethree dots in the lower right-hand corner of FIG. 5 indicate that theTrellis diagram can be extended for more than three clock cycles.

[0044] Each line drawn between any two of the dots in FIG. 5 representsan allowable transition between states for the 4-state FSM 40. Forexample, the line drawn between the dot at the top of the column at timeT₀ and the dot at the top of the column at time T₁ represents atransition between state S0 58 and S0. A further example is the linedrawn between the dot which is second from the top of the column at timeT₀ and the dot at the bottom of the column at time T₁ which represents atransition from state S1 60 to state S3 64.

[0045] Similar to the 4-state FSM 40 previously discussed, FIG. 6 is ablock diagram that illustrates an exemplary embodiment of a TCM encoder18 having an 8-state FSM 68. The TCM encoder generates a triple-bitoutput signal comprised of bits Z_(n) ², Z_(n) ¹, and Z_(n) ⁰ which aretransmitted from the transmitter 14. The 8-state FSM can be implementedusing three single-bit wide delay registers 70,72, and 74 and two adders76 and 78. Each single-bit wide delay register delays the signal inputto the delay register by one clock cycle designated by the letter “T.”FIG. 6 also shows the bits S_(n) ², S_(n) ¹, and S_(n) ⁰ that representthe current state of the 8-state FSM. S_(n) ² is the most significantbit and S_(n) ⁰ is the least significant bit of the current state.

[0046] In operation, a double-bit data signal comprising X_(n) ¹ andX_(n) ⁰, that is part of the data payload 28, is fed into the TCMencoder. The most significant input signal bit X_(n) ¹ becomes the mostsignificant bit Z_(n) ² of the output signal. Also, the input signal bitX_(n) ⁰ becomes the output signal bit Z_(n) ¹. The least significantoutput bit Z_(n) ⁰ equals the least significant current state bit S_(n)⁰. The 8-state FSM 68 equates the least significant current state bitS_(n) ⁰ to the sum of the least significant input bit X_(n) ⁰ andcurrent state bit S_(n) ¹ delayed by one clock cycle as a result of thesingle-bit wide delay register 74. The 8-state FSM equates the S_(n) ¹bit to the sum of the most significant input bit X_(n) ⁰ and currentstate bit S_(n) ² delayed by one clock cycle as a result of thesingle-bit wide delay register 72. Furthermore, the current state bitS_(n) ² equals the current state bit S_(n) ⁰ bit delayed by one clockcycle as a result of the single-bit wide delay register 70.

[0047]FIG. 7 is a table which lists the current state bits 84 for the8-state FSM 68 represented by S_(n) ², S_(n) ¹, and S_(n) ⁰, the inputsignal bits 86 represented by X_(n) ¹ and X_(n) ⁰, the output signalbits 88 represented by Z_(n) ², Z_(n) ¹, and Z_(n) ⁰, and the next statebits 90 for the 8-state FSM represented by S_(n+1) ², S_(n+1) ¹, andS_(n+1) ⁰. In operation, the 8-state FSM shown in FIG. 6 generates itsnext state represented by bits S_(n+1) ², S_(n+1) ¹, and S_(n+1) ⁰ basedupon the input signal bits X_(n) ¹ and X_(n) ⁰ and the 8-state FSM'scurrent state represented by bits S_(n) ², S_(n) ¹, and S_(n) ⁰. Forexample, if the current state of the 8-state FSM as represented by bitsS_(n) ², S_(n) ¹, and S_(n) ⁰ is {1 0 0}, and the input signal bitsX_(n) ¹ and X_(n) ⁰ are {1 0 }, the output signal bits Z_(n) ², Z_(n) ¹,and Z_(n) ⁰ are {1 0 0} and the next state bits are S_(n+1) ², S_(n+1)¹, and S_(n+1) ⁰ are {0 0 0}. FIG. 7 also indicates the limitations onchange of state from the current state represented by bits S_(n) ²,S_(n) ¹, and S_(n) ⁰ to the next state represented by bits S_(n+1) ²,S_(n+1) ¹, and S_(n+1) ⁰. For example, if the current state is {0 0 0},then the next state can only be {0 0 0}, if the input signal bits X_(n)¹ and X_(n) ⁰ are {0 0}, {0 0 1} when the input signal bits X_(n) ¹ andX_(n) ⁰ are {0 1}, {0 1 0} when the input signal bits X_(n) ¹ and X_(n)⁰ are {0 1}, or {0 1 1} if the input signal bits X_(n) ¹ and X_(n) ⁰ are{1 1}.

[0048] The limitation on the change of state in the 8-state FSM 68 isfurther represented by the Trellis diagram shown in FIG. 8. Analogous toFIG. 5, each of the 8 states of the 8-state FSM in FIG. 8 is given analphanumeric identifier comprised of the letter “S” and a decimal numberwhich equals the binary representation of the state. The identifier S092 is assigned to state {0 0 0}, the identifier S1 94 is assigned tostate {0 0 1}, the identifier S2 96 is assigned to state {0 1 0}, theidentifier S3 98 is assigned to state {0 1 1}, the identifier S4 100 isassigned to state {1 0 0}, the identifier S5 102 is assigned to state {10 1}, the identifier S6 104 is assigned to state {1 1 0}, and theidentifier S7 106 is assigned to state {1 1 1}.

[0049] Starting from the left-hand side of FIG. 8, the first verticalcolumn of dots, adjacent the identifiers, represents the states of the8-state FSM 68 at time T₀. Moving to the right, the next vertical columnof dots represents the states of the 8-state FSM at time T₁ which is oneclock cycle after T₀. Similarly, the next vertical column of dots to theright represents the states of the 8-state FSM at time T₂ which is twoclock cycles after T₀. The vertical column of dots furthest to the rightin FIG. 8 represents the states of the 8-state FSM at time T₃ which isthree clock cycles after T₀. The three dots in the lower right-handcorner of FIG. 8 indicate that the Trellis diagram can be extended tomore than three clock cycles.

[0050] Each line drawn between any two of the dots in FIG. 8 representsan allowable transition between states for the 8-state FSM 68. Forexample, the line drawn between the dot at the top of the column at timeT₀ and the dot at the top of the column at time T₁ represents atransition between state S0 92 and S0. A further example is the linedrawn between the dot second from the top of the column at time T₀ andthe dot at the bottom of the column at time T₁ which represents atransition from state S1 94 to state S7 106.

[0051] As stated previously, in order for a receiver to accuratelydecode burst transmissions of TCM encoded information, the MLSD shouldreceive a completed sequence of states. This is accomplished by means ofa string of bits that comprise the “Trellis tail” 32 that is appended atthe end of the frame 36 as shown in FIG. 2. The described exemplaryembodiment is directed to a Trellis tail for burst transmissions ofinformation encoded by a TCM encoder 18 having a 2 ^(p)-state FSM, wherep is any integer greater than one.

[0052] The following discussion applies the described exemplaryembodiment to a TCM encoding scheme utilizing a 4-state FSM 40. Asstated previously, FIG. 5 illustrates the Trellis diagram for a 4-stateFSM based on the state transitions given in FIG. 4. S0 58, S1 60, S2 62,and S3 64 represent the current states of the 4-state FSM denoted by {00}, {0 1 }, {1 0}, and {1 1}, respectively, as listed in FIG. 4. Afterexamining FIG. 5, one notices that there are various ways to bring theTrellis code to a known final state. Specifically, any one of thestates; S0, S1, S2, or S3 can be chosen as the final state. Furthermore,a variety of different state transitions can be selected to bring the4-state FSM to any one of the known final states.

[0053]FIG. 9 is a Trellis diagram showing one embodiment for a TCMencoding scheme implementing a 4-state FSM 40. Similar to FIG. 5, theallowable transitions between states of the 4-state FSM are designatedby lines. The Trellis tail 108 that constitutes this embodiment isrepresented by the state transitions between times T₁ and T₂, and alsobetween times T₂ and T₃.

[0054] The methodology for selecting the state transitions in thisembodiment for a 4-state FSM 40 is described as follows. If the currentstate of the 4-state FSM, at time T₁, includes an even number, i.e., S058 or S2 62, then the first transition, ending at time T₂, is made tostate S0 and the second transition, ending at time T₃, is made to stateS0 again. If the current state of the 4-state FSM, at time T₁, includesan odd number, i.e., S1 60 or S3 64, then the first transition, endingat time T₂, is made to state S2 and the second transition ending at timeT₂ is made to state S0. In this manner, the Trellis tail 108 appended atthe end of the frame 36 always ends the frame at the known state S0.

[0055]FIG. 10 is a chart that lists the current state 110 of the 4-stateFSM 40 at time T₁, i.e., at the end of the payload. FIG. 10 furthershows the first input bit X_(n) ⁰ 112 of the Trellis tail 108 that isinput to the TCM encoder and the second input bit X_(n) ⁰ 114 of theTrellis tail that is input to the TCM encoder to force the end of theTrellis tail to the known state S0. FIG. 10 illustrates a generalizedconcept that can be exploited to implement at least one embodiment ofthe TCM encoder. That is, regardless of the state of the 4-state FSM atT₁, if the binary representation of that state is used as serial inputbits to the TCM encoder, the end of the Trellis tail will be forced tothe known state S0 in two clock cycles. By way of example, if the stateof the 4-state FSM at T₁ is S1, then the end of the Trellis tail can beforced to the known state S0 by using the binary representation of thatstate {0,1} as the serial inputs to the TCM encoder. Specifically, attime T₁, X_(n) ⁰ is forced to a value corresponding to the MSB of thebinary representation of the state S1 {0}, and at time T₂, X_(n) ⁰ isforced to a value corresponding to the LSB of the binary representationof the state S1 {1}.

[0056] The precise implementation for controlling the inputs to the TCMencoder can take on various forms depending on the specific applicationand overall design constraints. An exemplary embodiment of a TCM encoderthat controls the inputs accordingly is shown in FIG. 11. The exemplaryTCM encoder 115 is a 4-state FSM 117 with feedback. The TCM encoder 115generates a double-bit encoded output signal comprised of bits Z_(n) ¹and Z_(n) ⁰ which are transmitted from the transmitter 14. The 4-stateFSM 117 can be implemented using two single-bit wide delay registers 119and 121, an interface 123. Each single-bit wide delay register delaysthe signal input to the delay register by one clock cycle, representedby the letter “T.” FIG. 11 also shows the bits S_(n) ¹ and S_(n) ⁰ thatrepresent the current state of the 4-state FSM. S_(n) ¹ is the mostsignificant bit and S_(n) ⁰ is the least significant bit of the currentstate.

[0057] In operation, a single-bit data signal D_(n) ⁰, that is part ofthe data payload, is fed into the interface 125. In the describedexemplary, the interface can be a switch, however, as those skilled inthe art will recognize, the interface can be implemented in any fashionin accordance with the general principles described herein. The switchis controlled by SELECT0, a signal sent from the transmit control unit20. Also, bit S_(n) ¹ is fed into the other input of the switch. WhenSELECT0 is logic level low, the data signal bit D_(n) ⁰ is fed throughthe switch becoming input signal bit X_(n) ⁰. In contrast, when SELECT0is logic level high, bit S_(n) ¹ is selected to pass through the switch.As shown FIG. 11, the input signal bit X_(n) ⁰ also becomes the mostsignificant bit Z_(n) ¹ of the encoded output signal. Also, the leastsignificant output bit Z_(n) ⁰ equals the least significant currentstate bit S_(n) ⁰ which the 4-state FSM 117 equates to the sum of theinput bit X_(n) ⁰ and the most significant current state bit S_(n) ¹delayed by one clock cycle as a result of the single-bit wide delayregister 121. Furthermore, the S_(n) ¹ bit equals the S_(n) ⁰ bitdelayed by one clock cycle as a result of the single-bit wide delayregister 119.

[0058] In this embodiment, the most significant bit S_(n) ¹ of thecurrent state is fed back into the TCM encoder and selected as the nextinput signal bit X_(n) ⁰ (in FIG. 9, the value of the input signal bitX_(n) ⁰ is shown adjacent each line representing a transition betweenstates). Thus, in this embodiment, the Trellis tail 108 is created bymerely feeding back the most significant bit of the current state bitsas the first input signal bit to generate the next state, and thenfeeding back the most significant bit of the next state bits as thesecond input signal bit. In this manner, no matter what state the4-state FSM is in at time T₁ the TCM encoder's 4-state FSM winds up instate S0 58 after two clock cycles, as shown in FIG. 9.

[0059]FIG. 12 is a Trellis diagram showing a Trellis tail that is analternative embodiment for a TCM encoding scheme using a 4-state FSM. Inthis embodiment, instead of feeding back the most significant bit S_(n)¹ of the current state into the TCM encoder with feedback 38 as the nextinput signal bit X_(n) ⁰ as was the case in the Trellis diagram shownFIG. 9, the complement of current state bit S_(n) ¹ is fed into the TCMencoder with feedback and selected as the next input signal bit X_(n) ⁰(in FIG. 12, the input signal bit X_(n) ⁰ is shown adjacent each linerepresenting a transition between states). Thus, in this embodiment, theTrellis tail is created by merely feeding back the complement of themost significant bit of the current state bits as the first input signalto generate the next state bits, and then feeding back the complement ofthe most significant bit of the next state bits as the second inputsignal bit. In doing so, the 4-state FSM winds up in state S3 64 aftertwo clock cycles no matter what state the 4-state FSM is in at time T₁.Thus, in this embodiment, if the current state of the 4-state FSMincludes an even number, i.e., S0 58 or S2 62, at time T₁, then the4-state FSM transitions to state S1 60 at time T₂ and then transitionsto state S3 at time T₃. Also, if the current state of the 4-state FSMincludes an odd number, i.e., S1 or S3, at time T₁, then the 4-state FSMtransitions to state S3 at time T₂ and then transitions again to stateS3 at time T₃. In this manner, the TCM encoder's 4-state FSM winds up instate S3 after two clock cycles regardless of the state of the 4-stateFSM at time T₁.

[0060] As was the case in FIG. 10, FIG. 13 is a chart that lists thecurrent state 110 of the 4-state FSM 40 at time T₁, the first input bitX_(n) ⁰ 112 of the Trellis tail 118 that is input to the TCM encoder 38at time T₁, and the second input bit X_(n) ⁰ 114 of the Trellis tailthat is input to the encoder at time T₂. FIG. 12 illustrates thatregardless of the state of the 4-state FSM at T₁, if the complement ofthe binary representation of that state is used as serial input bits tothe TCM encoder, the end of the Trellis tail will be forced to the knownstate S3 in two clock cycles. By way of example, if the state of the4-state FSM at T₁, is S1, then the end of the Trellis tail can be forcedto the known state S3 by using the compliment of he binaryrepresentation of that state {1,0} as the serial inputs to the TCMencoder. Specifically, at time T₁, X_(n) ⁰ is forced to a valuecorresponding to the MSB of the complement of the binary representationof the state S1 {1}, and at time T₂, X_(n) ⁰ is forced to a valuecorresponding to the LSB of the compliment of the binary representationof the state S1 {0}.

[0061] The described exemplary embodiment can also be applied to a TCMencoder 127 using an 8-state FSM. FIG. 14 is a Trellis diagram showing aTrellis tail 122 for the described exemplary TCM encoder utilizing an8-state FSM. As is the case in the other Trellis diagrams, the allowabletransitions between states are designated by lines. The Trellis tailthat constitutes this embodiment for an 8-state FSM is represented bythe transitions between times T₁, and T₂, and the transitions betweentimes T₂ and T₃.

[0062] The methodology for selecting the state transitions in thisembodiment for an 8-state FSM 68 is described as follows. If the currentstate of the 8-state FSM at time T₁ includes an even number, i.e., S092, S2 96, S4 100, or S6 104, then the first transition of the 8-stateFSM, ending at time T₂, is to state S0, and the second transition,ending at time T₃, is made to state S0 again. If the current stateincludes an odd number, i.e., S1 94, S3 98, S5 102, or S7 106, then thefirst transition, ending at time T₂, is made to state S4 and the secondtransition, ending at time T₃, is made to state S0. In this manner, theTrellis tail 122, appended at the end of frame 36, always returns theTCM encoder's 8-state FSM to the known state S0 after two clock cycles.

[0063]FIG. 15 is a chart that lists the current state 124 of the 8-stateFSM 68 at time T₁, the first input bits X_(n) ¹ and X_(n) ⁰ 126 of theTrellis tail 122 that are input to the TCM encoder with feedback 66 attime T₁, and the second input bits X_(n) ¹ and X_(n) ⁰ 128 of theTrellis tail that are input to the TCM encoder with feedback at time T₂.FIG. 15 illustrates a variation of the generalized concept discussedpreviously in connection with FIG. 10. That is, regardless of the stateof the 8-state FSM at T₁, if the binary representation if the binaryrepresentation of that state is used as serial input bits to the TCMencoder followed by a serial bit having a value {0}, the end of theTrellis tail will be forced to the known state S0 in two clock cycles.By way of example, if the state of the 4-state FSM at T₁ is S2, then theend of the Trellis tail can be forced to the known state S0 by using thebinary representation of that state {0,1,0} as the serial inputs to theTCM encoder followed by a serial bit {0}. Specifically, at time T₁,X_(n) ¹ is forced to a value corresponding to the MSB of the binaryrepresentation of the state S2 {0}, and X_(n) ⁰ is forced to a valuecorresponding to the second MSB of the binary representation of thestate S2 {1}. At time T₂, X_(n) ¹ is forced to a value corresponding tothe LSB of the binary representation of the state S1 {0}, and X_(n) ⁰ isforced to the bit {0}.

[0064] The 8-state FSM TCM encoder can be implemented in a variety ofways depending upon the system application and overall designconstraints. By way of example, a feedback methodology can be employedsimilar to that described in connection with a 4-state FSM TCM encoder.An exemplary TCM encoder with feedback is shown in FIG. 16. A TCMencoder 127 employs a feedback loop to control the input bits during thegeneration of the trellis tail. The TCM encoder generates a triple-bitoutput signal comprised of bits Z_(n) ², Z_(n) ¹, and Z_(n) ⁰ which aretransmitted from the transmitter. The 8-state FSM can be implementedusing three single-bit wide delay registers 131, 133, and 135, twoadders 137 and 139, and an interface 141. Each single-bit wide delayregister delays the signal input to the delay register by one clockcycle designated by the letter “T” FIG. 16 also shows the bits S_(n) ²,S_(n) ¹, and S_(n) ⁰ that represent the current state of the 8-stateFSM. S_(n) ² is the most significant bit and S_(n) ⁰ is the leastsignificant bit of the current state.

[0065] In operation, a double-bit data signal, comprised of bits D_(n) ¹and D_(n) ⁰, that is part of the data payload is fed into the interface141. In the described exemplary, the interface can be two switches 143and 145, however, as those skilled in the art will recognize, theinterface can be implemented in any fashion in accordance with thegeneral principles described herein. Data signal bit D_(n) ⁰ is fed intoan input of a first switch 143. The first switch is controlled bySELECT0, a signal sent from the transmit control unit. Also, bit S_(n) ¹is fed into the other input of the first switch. When SELECT0 is logiclevel low, the data signal bit D_(n) ⁰ is fed through the first switchbecoming input signal X_(n) ⁰. In contrast, when SELECT0 is logic levelhigh, S_(n) ¹ is selected to pass through the first switch. Data signalbit D_(n) ¹ is fed into an input of a second switch 145 which may be amultiplexer. The second switch is controlled by SELECT1, another signalsent from the transmit control unit. S_(n) ² is fed into the other inputof the second switch. When SELECT1 is logic level low, the data signalbit D_(n) ¹ is fed through the second switch becoming input signal X_(n)¹. On the other hand, when SELECT1 is logic level high, S_(n) ² isselected to pass through the second switch.

[0066] As a result of the described operation of the exemplary TCMencoder, the most significant input signal bit X_(n) ¹ becomes the mostsignificant bit Z_(n) ² of the output signal. Also, the input signal bitX_(n) ² becomes the output signal bit Z_(n) ¹. The least significantoutput bit Z_(n) ⁰ equals the least significant current state bit S_(n)⁰. The 8-state FSM 129 equates the least significant current state bitS_(n) ⁰ to the sum of the least significant input bit X_(n) ⁰ andcurrent state bit S_(n) ¹ delayed by one clock cycle as a result of thesingle-bit wide delay register 74. The 8-state FSM equates the S_(n) ¹bit to the sum of the most significant input bit X_(n) ¹ and currentstate bit S_(n) ² delayed by one clock cycle as a result of thesingle-bit wide delay register 133. Furthermore, the current state bitS_(n) ² equals the current state bit S_(n) ⁰ bit delayed by one clockcycle as a result of the single-bit wide delay register 131.

[0067] In this embodiment, the current state is represented by threebits S_(n) ², S_(n) ¹, and S_(n) ⁰. The two most significant bits S_(n)²and S_(n) ¹ of the 8-state FSM's current state bits are fed back intothe TCM encoder and selected as the next input signal bits X_(n) ¹ andX_(n) ⁰ respectively (in FIG. 14, the input signal bits X_(n) ¹ andX_(n) ⁰ are shown adjacent each line representing a transition betweenstates for the Trellis tail 122). Thus, in this embodiment, the Trellistail is created by merely feeding back the two most significant bits ofthe 8-state FSM's current state bits as the first input signals bitsused to generate the next state bits, and then feeding back the two mostsignificant bits of the 8-state FSM's next state bits as the secondinput signal bits. In this manner, no matter what state the 8-state FSMis in at time T₁ the 8-state FSM winds up in state S0 92 after two clockcycles as shown in FIG. 14.

[0068] As explained previously, the interface for the 4-state and8-state FSM TCM encoder can be implemented in a variety of fashions tocontrol the serial input bits to the TCM encoder during the generationof the Trellis tail. By way of example, the interface can be implementedwith a multiplexer. Alternatively, the interface can be implemented witha parallel-to-serial shift register which loads the state of the FSM atthe end of the payload and feeds serially the parallel loaded data intothe FSM during the Trellis tail generation. During the generation of thepreamble, payload and CRC, the data can be either clocked into a serialinput to the parallel-to-serial shift register or multiplexed with theoutput of the parallel-to-serial register. The interface could also beimplemented using a look-up table having an output that follows the dataoutput from the transmitter during the preamble, payload and CRC portionof the frame, and follows the serial sequence of the binaryrepresentation of the state of the FSM at the end of the payload duringthe generation of the Trellis tail. Numerous other implementations willreadily be apparent to those skilled in the art, and therefore, arewithin the scope of the present invention.

[0069]FIG. 17 is a Trellis diagram showing another Trellis tail 134 thatconstitutes an alternative embodiment for an 8-state FSM 68. In thisembodiment, instead of feeding back the two most significant bits S_(n)² and S_(n) ¹ of the 8-state FSM's current state into the TCM encoder asthe next input signal bits X_(n) ¹ and X_(n) ⁰, as was the case in theTrellis diagram shown in FIG. 16, the complement of bit S_(n) ² is fedinto the TCM encoder and selected as the next input signal bit X_(n) ¹and the complement of bit S_(n) ¹ is fed into the TCM encoder andselected as the next input signal bit X_(n) ⁰ (in FIG. 14, the inputsignal bits X_(n) ¹ and X_(n) ⁰ are shown adjacent each linerepresenting a transition between states). Thus, in this embodiment, theTrellis tail is created by merely feeding back the complement of the twomost significant bits of the 8-state FSM's current state bits as thefirst input signal bits used to generate the next state bits, and thenfeeding back the complement of the two most significant bits of the8-state FSM's next state bits as the second input signal bits. In doingso, the 8-state FSM winds up in state S7 106 after two clock cycles nomatter what the state of the 8-state FSM at time T₁. Thus, in thisembodiment, if the current state of the 8-state FSM includes an oddnumber, i.e., S1 94, S3 98, S5 102, or S7, at time T₁, then the 8-stateFSM transitions to state S7 at time T₂, and again to state S7 at timeT₃. Also, if the current state of the 8-state FSM includes an evennumber, i.e., S0 92, S2 96, S4 100, or S6 104, at time T₁, then the8-state FSM transitions to state S3 at time T₂ and then to state S7 attime T₃.

[0070] Similar to FIG. 15, FIG. 18 is a chart that lists the currentstate 124 of the 8-state FSM 68 at time T₁, the first input bits X_(n) ¹and X_(n) ⁰ 126 of the Trellis tail 134 that are input to the TCMencoder at time T₁, and the second input bits X_(n) ¹ and X_(n) ⁰ 128 ofthe Trellis tail that are input to the TCM encoder with feedback at timeT₂. FIG. 18 illustrates that regardless of the state of the 8-state FSMat T₁, if the complement of the binary representation of that statefollowed by a bit value {0} is used as serial input bits to the TCMencoder, the end of the Trellis tail will be forced to the known stateS7 in two clock cycles. By way of example, if the state of the 8-stateFSM at T₁, is S4, then the end of the Trellis tail can be forced to theknown state S7 by using the compliment of the binary representation ofthat state {0,1,1} followed by the bit value {0} as the serial inputs tothe TCM encoder. Specifically, at time T₁, X_(n) ¹ is forced to a valuecorresponding to the MSB of the complement of the binary representationof the state S4 {0}, and X_(n) ⁰ is forced to a value corresponding tothe second MSB of the complement of the binary representation of thestate S4 {1}. At time T₂, X_(n) ¹ is forced to a value corresponding tothe LSB of the compliment of the binary representation of the state S4{1}, and X_(n) ⁰ is forced to the {0} bit value.

[0071] Further embodiments of Trellis tails 32 are created by extendingthe above discussion to a TCM encoder 18 having a 2^(p)-state FSM, wherep is an integer greater than one. The TCM encoder accepts an inputsignal represented by input signal bits X_(n) ^(p-2), X_(n) ^(p-3), . .. , X_(n) ¹ and X_(n) ⁰ and generates an output signal represented byoutput signal bits Z_(n) ^(p-1), Z_(n) ^(p-2), . . . , Z_(n) ¹, andZ_(n) ⁰, and the 2^(p)-state finite state machine has a current staterepresented by current state bits S_(n) ^(p-1), S_(n) ^(p-2), . . . ,S_(n) ¹, and S_(n) ⁰ and a next state represented by next state bitsS_(n+1) ^(p-1), S_(n+1) ^(p-2), . . . , S_(n+1) ¹, and S_(n+1) ⁰

[0072] The described exemplary embodiments result in two embodiments ofa Trellis tail 32 for each 2 ^(p)-state FSM. In one embodiment, the p-1most significant bits of the current state bits are fed back into theTCM encoder 18 as input signal bits, respectively. Thus, in thisembodiment, the Trellis tail is created by merely feeding back the p-1most significant bits of the 2 ^(p)-state FSM's current state bits asthe first input signal bits used to generate the next state bits, andthen feeding back the p-1 most significant bits of the 2 ^(p)-stateFSM's next state bits as the second input signal bits. This results in aTrellis tail that transitions the current state of the transmitter's 2^(p)-state FSM to state S0 within two clock cycles regardless of thecurrent state before the clock cycles.

[0073] In operation, if the current state of the 2 ^(p)-state FSM beforethe clock cycles includes an even number, i.e., S0, S2, S4, . . . , S2^(p)-2, the Trellis tail 32 transitions the 2 ^(p)-state FSM to state S0after the first clock cycle and remain at state S0 after the secondclock cycle. Also, when the current state of the 2 ^(p)-state FSM beforethe clock cycles includes an odd number, i.e., S1, S3, S5, . . . , S2^(p)-1, the 2 ^(p)-state FSM transitions to state S2 ^(p-1) after oneclock cycle. The next transition results in the 2 ^(p)-state FSM movingto state S0 after the second clock cycle. Thus, the 2 ^(p)-state FSMwinds up in state S0 after two clock cycles regardless of the state ofthe 2 ^(p)-state FSM before the clock cycles. Furthermore, if the secondinput signal just prior to the second clock cycle is appended to thefirst input signal just prior to the first clock cycle, the p mostsignificant bits of the resulting 2p-2-bit long binary number constitutethe binary form of the decimal equivalent to the current state of the 2^(p)-state FSM before the first clock cycle. Also, the p-2 leastsignificant bits of the 2p-2-bit number are always 0.

[0074] Other embodiment of the Trellis tail 32, including a 2 ^(p)-stateFSM where p is an integer that equals the number of current state bitsS_(n) ^(p-1), S_(n) ^(p-2), . . . , S_(n) ¹, and S_(n) ⁰, occurs wherethe compliment of each of the p-1 most significant bits of the currentstate are fed back into the TCM encoder 18 as the input signal bits,respectively. Thus, in this embodiment, the Trellis tail is created bymerely feeding back the complement of the p-1 most significant bits ofthe 2 ^(p)-state FSM's current state bits as the first input signal bitsused to generate the next state bits, and then feeding back thecomplement of the p-1 most significant bits of the 2 ^(p)-state FSM'snext state bits as the second input signal bits. This results in aTrellis tail which transitions the TCM encoder's 2 ^(p)-state FSM tostate S2 ^(p)-1 after two clock cycles regardless of the current statebefore the clock cycles.

[0075] In operation, if the current state of the 2 ^(p)-state FSM beforethe clock cycles is an odd number, i.e., S1, S3, S5, . . . , S2 ^(p)-1,the Trellis tail 32 transitions the 2 ^(p)-state FSM to state S2 ^(p)-1after one clock cycle. After a second clock cycle, the 2 ^(p)-state FSMtransitions again to state S2 ^(P)-1. In contrast, if the current stateof the 2 ^(p)-state FSM before the clock cycles is an even number, i.e.,S0, S2, S4, . . . , S2 ^(p)-2, then the next state of the 2 ^(p)-stateFSM after one clock cycle is state S2 ^((p-1))-1. After the second clockcycle, the 2 ^(p)-state FSM transitions to state S2 ^(p)-1. Thus, the 2^(p)-state FSM winds up in state S2 ^(p)-1 after two clock cyclesregardless of the state of the 2 ^(p)-state FSM before the clock cycles.Also, if the second input signal just prior to the second clock cycle isappended to the first input signal just prior to the first clock cycle,the p most significant bits of the resulting 2p-2 bit long binary numberconstitute the complement of the binary form of the decimal equivalentto the current state of the 2 ^(p)-state FSM before the first clockcycle. Also, the p-2 least significant bits of the 2p-2-bit number arealways 0.

[0076] Therefore, the various embodiments described herein are Trellistails 32 having the unique and nonobvious feature that for a 2^(p)-state FSM, where p is an integer that equals the number of currentstate bits S_(n) ^(p-1), S_(n) ^(p-2), . . . , S_(n) ¹, and S_(n) ⁰, ifthe second input signal just prior to the second clock cycle is appendedto the first input signal just prior to the first clock cycle the p mostsignificant bits of the resulting 2p-2 bit long binary number constitutethe binary form, or the complement of the binary form depending upon theembodiment, of the decimal equivalent to the current state of the 2^(p)-state FSM before the first clock cycle. Thus, the p-1 mostsignificant bits of the 2 ^(p)-state FSM's current state, or theircomplements, are merely fed back into the TCM encoder 18 as the inputdata bits. In doing so, the Trellis tails, within two clock cycles,transitions the TCM encoder's 2 ^(p)-state FSM to one of two knownstates, either S0 or S2 ^(p)-1 depending upon the described exemplaryembodiment.

[0077] Although exemplary embodiments of the present invention has beendescribed, it should not be construed to limit the scope of the appendedclaims. Those skilled in the art will understand that variousmodifications may be made to the described embodiments. Moreover, tothose skilled in the various arts, the invention itself herein willsuggest solutions to other tasks and adaptions for other applications.It is therefore desired that the present embodiments be considered inall respects as illustrative and not restrictive, reference being madeto the appended claims rather than the foregoing description to indicatethe scope of the invention.

What is claimed is:
 1. An encoder, comprising: a state machineconfigured to generate a plurality of state bits; and an interfaceconfigured to couple an input relating to one of the state bits into thestate machine during a time period.
 2. The encoder of claim 1 whereinthe interface comprises a switch.
 3. The encoder of claim 1 wherein theinterface is configured to couple an input signal into the state machineduring a second time period, and coupled said one of the state bits intothe state machine during the time period.
 4. The encoder of claim 1wherein the interface is configured to couple an input signal into thestate machine during a second time period, and couple a complement ofsaid one of the state bits into the state machine during the timeperiod.
 5. The encoder of claim 1 further comprising an output includinga second one of the state bits.
 6. The encoder of claim 5 wherein theinterface comprises an output, the encoder output further including theinterface output.
 7. The encoder of claim 1 wherein the state machinecomprises a 2 ^(p)-state finite state machine where p comprises aninteger greater than one.
 8. The encoder of claim 1 wherein the statemachine includes at least two delay registers configured to delay theplurality of state bits.
 9. The encoder of claim 8 wherein the statemachine includes an adder coupled to one of the delay registers.
 10. Anencoder, comprising: state generation means for generating a pluralityof state bits; and interface means for coupling an input relating to oneof the state bits into the state generation means during a time period.11. The encoder of claim 10 wherein the interface means comprises aswitch.
 12. The encoder of claim 10 wherein the interface means isconfigured to couple an input signal into the state generation meansduring a second time period, and coupled said one of the state bits intothe state machine during the time period.
 13. The encoder of claim 10wherein the interface means is configured to couple an input signal intothe state generation means during a second time period, and coupled acomplement of said one of the state bits into the state machine duringthe time period.
 14. The encoder of claim 10 further comprising anoutput including a second one of the state bits.
 15. The encoder ofclaim 14 wherein the interface comprises an output, the encoder outputfurther including the interface output.
 16. The encoder of claim 10wherein the state generation means comprises a 2 ^(p)-state finite statemachine where p is an integer greater than one.
 17. The encoder of claim10 wherein the state generation means includes at least two delayregisters configured to delay the plurality of state bits.
 18. Theencoder of claim 17 wherein the state generation means includes an addercoupled to one of the delay registers.
 19. A transmitter, comprising: anencoder having, a state machine configured to generate a plurality ofstate bits, and an interface configured to couple an input relating toone of the state bits into the state machine during a time period; andan RF stage coupled to the encoder.
 20. The encoder of claim 19 whereinthe interface comprises a switch.
 21. The encoder of claim 19 whereinthe interface is configured to couple an input signal into the statemachine during a second time period, and coupled said one of the statebits into the state machine during the time period.
 22. The encoder ofclaim 19 wherein the interface is configured to couple an input signalinto the state machine during a second time period, and coupled acomplement of said one of the state bits into the state machine duringthe time period.
 23. The encoder of claim 19 further comprising anoutput including a second one of the state bits.
 24. The encoder ofclaim 23 wherein the interface comprises an output, the encoder outputfurther including the interface output.
 25. The transmitter of claim 19wherein the state machine comprises a 2 ^(p)-state finite state machinewhere p comprises an integer greater than one.
 26. The transmitter ofclaim 19 wherein the state machine includes at least two delay registersconfigured to delay the plurality of state bits.
 27. The transmitter ofclaim 26 wherein the state machine includes an adder coupled to one ofthe delay registers.
 28. The transmitter of claim 19 further comprisinga transmit control unit coupled to the encoder, the transmit controlunit being configured to control the interface.
 29. The transmitter ofclaim 28 further comprising a preamble generator coupled to the transmitcontrol logic unit.
 30. The transmitter of claim 28 further comprising aCRC generator coupled to the transmit control logic unit.
 31. Atransmitter, comprising: an encoder having, state generation means forgenerating a plurality of state bits, and interface means for couplingan input relating to one of the state bits into the state generationmeans during a time period; and an RF stage coupled to the encoder. 32.The transmitter of claim 31 wherein the interface means comprises aswitch.
 33. The transmitter of claim 31 wherein the interface means isconfigured to couple an input signal into the state generation meansduring a second time period, and couple said one of the state bits intothe state machine during the time period.
 34. The transmitter of claim31 wherein the interface means is configured to couple an input signalinto the state generation means during a second time period, and couplea compliment of said one of the state bits into the state machine duringthe time period.
 35. The transmitter of claim 31 further comprising anoutput including a second one of the state bits.
 36. The transmitter ofclaim 3 5 wherein the interface comprises an output, the encoder outputfurther including the interface output.
 37. The transmitter of claim 31wherein the state generation means comprises a 2 ^(p)-state finite statemachine where p is an integer greater than one.
 38. The transmitter ofclaim 31 wherein the state generation means includes at least two delayregisters configured to delay the plurality of state bits.
 39. Thetransmitter of claim 3 8 wherein the state generation means includes anadder coupled to one of the delay registers.
 40. The transmitter ofclaim 31 further transmit control means for controlling the interfacemeans to couple the input relating to one of the state bits into thestate generation means during the time period; and
 41. The transmitterof claim 40 further comprising means for generating a preamble coupledto the transmit control means.
 42. The transmitter of claim 40 furthercomprising means for generating a CRC coupled to the transmit controlmeans.
 43. An encoder, comprising: a state machine configured togenerate a state; and an interface configured to serially couple aninput relating to a binary representation of the state into the statemachine during a time period. 44 The encoder of claim 43 wherein theinterface is configured to serially couple a plurality of input signalsinto the state machine during a second time period, and serially couplethe binary representation of the state at the end of the second periodinto the state machine during the time period. 45 The encoder of claim43 wherein the interface is configured to serially couple a plurality ofinput signals into the state machine during a second time period, andserially couple a compliment of the binary representation of the stateat the end of the second period into the state machine during the timeperiod.
 46. The encoder of claim 43 wherein the interface comprises aswitch configured to serially couple the input signals into the statemachine during the second time period, and serially couple the inputrelating to the binary representation of the state at the end of thesecond period into the state machine during the time period.
 47. Theencoder of claim 43 wherein the state machine comprises a 2 ^(p)-statefinite state machine where p comprises an integer greater than one. 48.The encoder of claim 43 wherein the state machine includes at least twodelay registers configured to generate the state.
 49. The encoder ofclaim 48 wherein the state machine includes an adder coupled to one ofthe delay registers.
 50. An encoder, comprising: state generation meansfor generating a state; and interface means for serially coupling aninput relating to a binary representation of the state into the statemachine during a time period.
 51. The encoder of claim 50 wherein theinterface means is configured to serially couple a plurality of inputsignals into the state generation means during a second time period, andserially couple the binary representation of the state at the end of thesecond period into the state generation means during the time period.52. The encoder of claim 50 wherein the interface comprises a switchconfigured to serially couple the input signals into the stategeneration means during the second time period, and serially couple acompliment of the binary representation of the state at the end of thesecond period into the state generation means during the time period.53. The encoder of claim 50 wherein the state generation means comprisesa 2 ^(p)-state finite state machine where p comprises an integer greaterthan one.
 54. The encoder of claim 50 wherein the state generation meansincludes at least two delay registers configured to generate the state.55. The encoder of claim 54 wherein the state generation means includesan adder coupled to one of the delay registers.
 56. A method ofgenerating a signal, comprising: generating a payload as a function of astate machine output; generating a tail as a function a binaryrepresentation of the state machine output at the end of the payloadgeneration; and appending the tail to the payload.
 57. The method ofclaim 56 wherein the state machine output comprises a plurality of statebits, the tail generation comprising serially feeding the state bits forthe binary representation of the state machine output at the end of thepayload generation into the state machine.
 58. The method of claim 56wherein the state machine output comprises a plurality of state bits,the tail generation comprising serially feeding a compliment for each ofthe state bits for the binary representation of the state machine outputat the end of the payload generation into the state machine.
 59. Themethod of claim 56 wherein the state machine output comprises aplurality of first state bits having a most significant bit, the tailgeneration comprising feeding the most significant bit of the firststate bits into the state machine during a first clock cycle to generatea second plurality of state bits having a most significant bit, andfeeding the most significant bit of the second state bits into the statemachine during a second clock cycle.
 60. The method of claim 59 whereinthe first state bits further comprise a least significant bit, andwherein the most significant bit of the second state bits is the leastsignificant bit of the first state bits.
 61. The method of claim 56wherein the state machine output comprises a plurality of first statebits having a most significant bit, the tail generation comprisingfeeding a compliment of the most significant bit of the first state bitsinto the state machine during a first clock cycle to generate a secondplurality of state bits having a most significant bit, and feeding acompliment of the most significant bit of the second state bits into thestate machine during a second clock cycle.
 62. The method of claim 61wherein the first state bits further comprise a least significant bit,and wherein the most significant bit of the second state bits is theleast significant bit of the first state bits.